Measurement of Thermal Stress by X-ray Nano-Diffraction in (111)-Oriented Nanotwinned Cu Bumps for Cu/SiO2 Hybrid Joints.

X-ray nanodiffraction was used to measure the thermal stress of 10 µm nanotwinned Cu bumps in Cu/SiO2 hybrid structures at -55 °C, 27 °C, 100 °C, 150 °C, and 200 °C. Bonding can be achieved without externally applied compression. The X-ray beam size is about 100 nm in diameter. The Cu bump is dominated by (111) oriented nano-twins. Before the hybrid bonding, the thermal stress in Cu bumps is compressive and remains compressive after bonding. The average stress in the bonded Cu joint at 200 °C is as large as -169.1 MPa. In addition, using the strain data measured at various temperatures, one can calculate the effective thermal expansion coefficient (CTE) for the 10 µm Cu bumps confined by the SiO2 dielectrics. This study reports a useful approach on measuring the strain and stress in oriented metal bumps confined by SiO2 dielectrics. The results also provide a deeper understanding on the mechanism of hybrid bonding without externally applied compression.

Low-Temperature Cu/SiO2 Hybrid Bonding with Low Contact Resistance Using (111)-Oriented Cu Surfaces.

We adopted (111)-oriented Cu with high surface diffusivity to achieve low-temperature and low-pressure Cu/SiO2 hybrid bonding. Electroplating was employed to fabricate arrays of Cu vias with 78% (111) surface grains. The bonding temperature can be lowered to 200 °C, and the pressure is as low as 1.06 MPa. The bonding process can be accomplished by a 12-inch wafer-to-wafer scheme. The measured specific contact resistance is 1.2 × 10-9 Ω·cm2, which is the lowest value reported in related literature for Cu-Cu joints bonded below 300 °C. The joints possess excellent thermal stability up to 375 °C. The bonding mechanism is also presented to provide more understanding on hybrid bonding.

Warpage Characteristics and Process Development of Through Silicon Via-Less Interconnection Technology.

In this study, through silicon via (TSV)-less interconnection using the fan-out wafer-level-packaging (FO-WLP) technology and a novel redistribution layer (RDL)-first wafer level packaging are investigated. Since warpage of molded wafer is a critical issue and needs to be optimized for process integration, the evaluation of the warpage issue on a 12-inch wafer using finite element analysis (FEA) at various parameters is presented. Related parameters include geometric dimension (such as chip size, chip number, chip thickness, and mold thickness), materials' selection and structure optimization. The effect of glass carriers with various coefficients of thermal expansion (CTE) is also discussed. Chips are bonded onto a 12-inch reconstituted wafer, which includes 2 RDL layers, 3 passivation layers, and micro bumps, followed by using epoxy molding compound process. Furthermore, an optical surface inspector is adopted to measure the surface profile and the results are compared with the results from simulation. In order to examine the quality of the TSV-less interconnection structure, electrical measurement is conducted and the respective results are presented.